This invention generally pertains to silicon-on-insulator (SOI) technology comprising thin-film semiconductor SOI devices formed on an insulating layer formed on a semiconductor substrate and more particularly to SOI CMOS devices.
SOI devices, such as CMOS FET devices, are formed on prepared insulating layers, such as SIMOX buried oxide layers prepared on semiconductor substrates. Then, an epitaxially deposited Si layer is formed on the oxide layer and CMOS thin-film transistors, e.g., n-channel MOS FET, p-channel MOS FET, are formed in the Si layer with polysilicon gates separated by a thin gate oxide self-aligned relative to the CMOS thin-film transistor channel. In other cases, the thin-film MOS FET are commonly formed relative to a substrate floating condition on a semiconductor film formed on an insulating film.
However, many problems still remain in SOI technology. As an example, the resultant physical and electrical properties of the thin-film semiconductor devices formed in the thin-film layer supported on the prepared insulating layer are not consistently uniform. This because of defects in and ion transfer to the thin-film semiconductor film resulting in film damage thereby affecting its electrical properties and reduce the performance of electrical components, e.g., n-channel MOS FETs, p-channel MOS FETs, formed in the thin films. As an example, the MOS FET threshold voltage of SOI thin-film devices formed in such thin-film semiconductor films will not consistently uniform.
Thus, it is a purpose of this invention to solve this problem by offering a thin-film SOI semiconductor device structure that will consistently yield more uniform electrical characteristics.
Further, in the case of the substrate floating effect of SOI MOS FET thin film semiconductor substrates or base layers formed over SIMOX films, particularly in the case of such devices submicron channel lengths, there is a corresponding decrease in breakdown voltage between the source and drain of such devices. This is referred to as short channeling wherein shortened channel length decreases threshold voltage. Thus, it is a further purpose of the present invention to offer an improved thin-film SOI MOS FET device that will not reduce the breakdown voltage between the source and drain at submicron channel lengths due to the substrate floating effect in SOI MOS FET thin film semiconductor substrates.
An ideal contact portion for a typical thin-film SOI semiconductor device is shown in cross section in FIG. 7. The contact structure comprises a Si semiconductor substrate 81, e.g., 500 .mu.m thick, upon which is formed, such as, by SIMOX, SiO.sub.2 film 82 which may have a thickness of about 0.5 .mu.m. Next, a n-Si film 83 is epitaxially deposited on SiO.sub.2 film 82 which may have a thickness in the range of about 30 nm to 50 nm which is usually employed for such TFTs. This is followed by the CVD deposition of SiO.sub.2 film 84 having a thickness in the range of about 0.5 .mu.m. Then contact hole 86 is formed in SiO.sub.2 film 84 by means of conventional wet etching. Lastly, metal or polysilicon electrode 85 is deposited over and in contact hole 86. However, when diameter of contact hole 86 is less than 2 .mu.m, then dry etching must be employed to obtain this resolution. However, when dry etching is employed, the etching process advances into the thin Si film 83 so that Si film 83 at the bottom of contact hole 86 was depleted or removed so that electrode connection was poor or nonexistent. In other words, it is difficult to control the etching through SiO.sub.2 film 84 without also etching away film 83 because end point detection is difficult to achieve in connection with such thin films when employing such a fast etching method to achieve better resolution at smaller scales. Also, any reliable contact to film 83 is not good when seeking to achieve surface contact 87 as the means for reliable contact. Thus, while the configuration shown in FIG. 7 with a large area contact at 87 to film 83 is ideally desired, it cannot be realized in practice, particularly for dimensions less than 2 .mu.m.
Thus, it is a further purpose of the present invention to offer an improved contact portion for a thin-film SOI semiconductor device of the type shown in FIG. 7 that will ensure reliable and consistently reproducible connection between the semiconductor thin-film and electrode in thin-film SOI semiconductor devices.